TXLVLENA=DISABLED, RXLVLENA=DISABLED
FIFO trigger settings for interrupt and DMA request.
| TXLVLENA | Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 (DISABLED): Transmit FIFO level does not generate a FIFO level trigger. 1 (ENABLED): An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. |
| RXLVLENA | Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 0 (DISABLED): Receive FIFO level does not generate a FIFO level trigger. 1 (ENABLED): An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. |
| TXLVL | Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). |
| RXLVL | Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). |